首先是宝藏网站WonderfulToolchain ，集中整理了很多你想知道和不知道的东西，其中就有个史诗级的开源卡带RSDuck/nileswan，集成了TF卡和usb，真担心它耗电厉害，主芯片采用的FPGA是ICE40HX1K-VQ100
2014年986-Studio/WonderMadeleine发布的WonderMadeleine is a Bandai 2001/2003 clone chip项目，成功做出了模拟卡带，用的是大家非常眼熟的EPM240T，
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C3
set_global_assignment -name TOP_LEVEL_ENTITY WonderMadeleine
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:43:30 OCTOBER 28, 2014"
只支持到sram。
-- What is currently working: (as of 13 november 2014) --
-- [X] - ROM Banking --
-- [X] - SRAM Banking --
-- [X] - WonderSwan boot unlock --
-- [ ] - EEPROM --
-- [ ] - RTC --
-- [ ] - GPIO --
-- [ ] - All other unknown parts --
卡带的接口定义：
== Memory access ==
Both the ROM and the SRAM chip use a standard asynchronous memory interface.
It is presumed that:
* the CPU sets the address lines before each memory access while '''/OE''' or '''/WE''' respectively are still high,
* for writes the CPU sets the data lines with the falling edge of '''/WE''' (TODO: only confirmed for I/O writes),
* for reads the CPU latches the data lines on the subsequent rising edge of '''/OE'''.
Memory may be accessed in 8-bit or 16-bit mode. SRAM reads/writes always happen in 8-bit mode, while ROM reads/writes can happen in 8-bit or 16-bit mode depending on [[ROM header|header]] configuration.
Note that in 16-bit mode, the output on address line '''A0''' is undetermined and should be ignored.
== Pinout ==
<pre>
Cartridge Console
(label side) (back)
____________
|====|
____ |--48| -- GND
... \ | -47| <- CLK
... | | -46| -> /IRQ (Interrupt request)
... | | -45| <- /SEL (Cartridge select)
... | | -44| <- /WR (Write enable)
... | | -43| <- /RD (Read enable)
... | | -42| <- M/IO (Memory/IO)
... | | -41| -> /MBC
... | | -40| <- /RESET
... | | -39| <> D13
... | | -38| <> D12
... | | -37| <> D11
... | | -36| <> D10
... | | -35| <> D9
... | | -34| <> D8
... | | -33| <- CPU A16
... | | -32| <- CPU A17
... | | -31| <- CPU A18
... | | -30| <- CPU A19
... | | -29| <- CPU A3
... | | -28| <- CPU A2
... | | -27| <- CPU A1
... | | -26| <- CPU A0
... | |--25| -- +3.3V
... | |--24| -- +3.3V
... | | -23| <> D0
... | | -22| <> D1
... | | -21| <> D2
... | | -20| <> D3
... | | -19| <> D4
... | | -18| <> D5
... | | -17| <> D6
... | | -16| <> D7
... | | -15| <> D14
... | | -14| <> D15
... | | -13| <- CPU A4
... | | -12| <- CPU A5
... | | -11| <- CPU A6
... | | -10| <- CPU A7
... | | -09| <- CPU A12
... | | -08| <- CPU A14
... | | -07| <- CPU A13
... | | -06| <- CPU A8
... | | -05| <- CPU A9
... | | -04| <- CPU A11
... | | -03| <- CPU A10
____/ | -02| <- CPU A15
|--01| -- GND
_______|====|
Cartridge Console
(label side) (back)
</pre>
== Mechanical details ==
{| class="wikitable"
|-
! Distance !! Length (in mm)
|-
| Distance pad to pad || 1.25
|-
| Left edge to first pad || 0.7
|-
| Last pad to right edge || 0.95
|-
| Bottom edge to longer pads (GND, Vcc) || 0.5
|-
| Bottom edge to shorter pads || 1
|}
== Signal descriptions ==
* '''/RESET''': Reset signal output from the console. On a mono WonderSwan, it stays low for about 18 milliseconds after power-up.
* '''/MBC''': Authentication handshake signal. A cartridge is required to communicate over this pin shortly after reset.
* '''M/IO''': Memory/IO bus selection. The cartridge bus allows both memory access (to physical addresses 0x10000-0xFFFFF) and I/O access (to ports 0xC0-0xFF):
** When Memory/IO is '''high''', pins A0-A19 specify the 20-bit linear memory address.
** When Memory/IO is '''low''', pins A0-A7 specify the 8-bit I/O port address, pins A8-A15 are low, pins A16-A19 are a copy of the I/O port address bits 4-7.
* '''/IRQ''': Cartridge interrupt. When this pin is pulled low, the console will trigger a maskable cartridge interrupt.
* '''CLK''': A clock provided by the console. This pin outputs a frequency of 384 KHz, derived from the 12.288 MHz system clock; on the WonderSwan Color, it can optionally be configured by software to provide a 6.144 MHz frequency instead.
== Timing requirements ==
The '''/OE''' or '''/WE''' signal appear to have a frequency of about 3.072 MHz, derived from the 12.288 MHz system clock. This leaves half this period, so about 162 ns, to handle one memory access.
TODO: Verify how using ROM/SRAM wait states affects this.
== Authentication handshake ==
Shortly after '''/RESET''' goes high, a handshake between the SoC and the cartridge is performed, in order:
* '''/MBC''' is held high. '''A0'''-'''A3''' are set to 0xA and '''A16'''-'''A19''' are set to 0x5.
* On a rising edge of '''CLK''', '''A0'''-'''A3''' are set to 0x5 and '''A16'''-'''A19''' are set to 0xA.
* The cartridge continues to hold '''/MBC''' high for three additional '''CLK''' rising edges. Note that the SoC appears to allow some variance in this number of cycles.
* For each subsequent rising edge of '''CLK''', the cartridge is expected to output the following binary sequence through its '''/MBC''' pin: <code>1000101000101000000111</code>.
* After this is finished, '''/MBC''' is expected to stay high indefinitely.
On a successful handshake, the [[SoC]] sets bit 7 of the System Control I/O port. The boot ROM will refuse to boot the cartridge if this bit is not set; on the WonderSwan Color, it will refuse to start the system at all.
An example public domain (CC0) VHDL implementation by trap15 is available [https://bitbucket.org/trap15/mbc-unlock here].
卡带dump和烧录器：up-n-atom/WonderSwanCartTap
基于VCC-GND STM32F103ZET6 Adapter Boards，这个开发板淘宝50块，可以读卡，可以烧录flash，作者有放源码，但是没打包。
卡带信息：master/hash/wswan.xml
卡带有至少3种类型，有的是sram，有的没有，有的实例：
<software name="anchorz">
<description>Anchorz Field</description>
<year>1999</year>
<publisher>Sammy</publisher>
<info name="serial" value="SWJ-SUM004"/>
<info name="release" value="19990624"/>
<info name="alt_title" value="アンカーズ・フィールド"/>
<part name="cart" interface="wswan_cart">
<feature name="pcb" value="PTE-0037" />
<feature name="u1" value="BANDAI 2001" />
<feature name="u2" value="GIZA" />你没看错，芯片叫吉萨，就是金字塔那儿
<feature name="u3" value="ROM" />
<feature name="u4" value="BS62LV256TC SRAM" />
<feature name="slot" value="ws_sram" />
<dataarea name="rom" size="1048576" width="16" endianness="little">
<rom name="mh8m256s033a.u3" size="1048576" crc="425eb893" sha1="06447c248afce04c4f4a1c3b5f7a4ab6f383c94b" offset="000000" />
</dataarea>
<dataarea name="sram" size="8192" width="16" endianness="little">
</dataarea>
</part>
</software>
<software name="cclimber">
<description>Crazy Climber</description>
<year>1999</year>
<publisher>Nihon Bussan</publisher>
<info name="serial" value="SWJ-NHB001"/>
<info name="release" value="19990729"/>
<info name="alt_title" value="クレイジー・クライマー"/>
<part name="cart" interface="wswan_cart">
<feature name="pcb" value="PTE-0012A" />
<feature name="u1" value="BANDAI 2001" />
<feature name="u2" value="empty" />
<feature name="u3" value="ROM" />
<feature name="slot" value="ws_rom" />
<dataarea name="rom" size="1048576" width="16" endianness="little">
<rom name="mh8m0e038a.u3" size="1048576" crc="0cb57376" sha1="a88882426bf435416616191902a26b2b066f2491" offset="000000" />
</dataarea>
</part>
</software>
<software name="engacho">
<description>Engacho! for WonderSwan</description>
<year>1999</year>
<publisher>Nihon Application</publisher>
<info name="serial" value="SWJ-NAP001"/>
<info name="release" value="19991028"/>
<info name="alt_title" value="えんがちょ! for ワンダースワン"/>
<part name="cart" interface="wswan_cart">
<feature name="pcb" value="PTE-0012A" />
<feature name="u1" value="BANDAI 2001" />
<feature name="u2" value="EEPROM" />
<feature name="u3" value="ROM" />
<feature name="slot" value="ws_eeprom" />
<dataarea name="rom" size="1048576" width="16" endianness="little">
<rom name="mh8m1e049a.u3" size="1048576" crc="4e467626" sha1="f79451034b6d844f0e10c825306bbc26f26a5466" offset="000000" />
</dataarea>
<dataarea name="eeprom" size="0x80" width="16" endianness="little">
</dataarea>
</part>
</software>
存档类型转换：splash5/ws-eeprom-to-sram-ips
2014年986-Studio/WonderMadeleine发布的WonderMadeleine is a Bandai 2001/2003 clone chip项目，成功做出了模拟卡带，用的是大家非常眼熟的EPM240T，
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C3
set_global_assignment -name TOP_LEVEL_ENTITY WonderMadeleine
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:43:30 OCTOBER 28, 2014"
只支持到sram。
-- What is currently working: (as of 13 november 2014) --
-- [X] - ROM Banking --
-- [X] - SRAM Banking --
-- [X] - WonderSwan boot unlock --
-- [ ] - EEPROM --
-- [ ] - RTC --
-- [ ] - GPIO --
-- [ ] - All other unknown parts --
卡带的接口定义：
== Memory access ==
Both the ROM and the SRAM chip use a standard asynchronous memory interface.
It is presumed that:
* the CPU sets the address lines before each memory access while '''/OE''' or '''/WE''' respectively are still high,
* for writes the CPU sets the data lines with the falling edge of '''/WE''' (TODO: only confirmed for I/O writes),
* for reads the CPU latches the data lines on the subsequent rising edge of '''/OE'''.
Memory may be accessed in 8-bit or 16-bit mode. SRAM reads/writes always happen in 8-bit mode, while ROM reads/writes can happen in 8-bit or 16-bit mode depending on [[ROM header|header]] configuration.
Note that in 16-bit mode, the output on address line '''A0''' is undetermined and should be ignored.
== Pinout ==
<pre>
Cartridge Console
(label side) (back)
____________
|====|
____ |--48| -- GND
... \ | -47| <- CLK
... | | -46| -> /IRQ (Interrupt request)
... | | -45| <- /SEL (Cartridge select)
... | | -44| <- /WR (Write enable)
... | | -43| <- /RD (Read enable)
... | | -42| <- M/IO (Memory/IO)
... | | -41| -> /MBC
... | | -40| <- /RESET
... | | -39| <> D13
... | | -38| <> D12
... | | -37| <> D11
... | | -36| <> D10
... | | -35| <> D9
... | | -34| <> D8
... | | -33| <- CPU A16
... | | -32| <- CPU A17
... | | -31| <- CPU A18
... | | -30| <- CPU A19
... | | -29| <- CPU A3
... | | -28| <- CPU A2
... | | -27| <- CPU A1
... | | -26| <- CPU A0
... | |--25| -- +3.3V
... | |--24| -- +3.3V
... | | -23| <> D0
... | | -22| <> D1
... | | -21| <> D2
... | | -20| <> D3
... | | -19| <> D4
... | | -18| <> D5
... | | -17| <> D6
... | | -16| <> D7
... | | -15| <> D14
... | | -14| <> D15
... | | -13| <- CPU A4
... | | -12| <- CPU A5
... | | -11| <- CPU A6
... | | -10| <- CPU A7
... | | -09| <- CPU A12
... | | -08| <- CPU A14
... | | -07| <- CPU A13
... | | -06| <- CPU A8
... | | -05| <- CPU A9
... | | -04| <- CPU A11
... | | -03| <- CPU A10
____/ | -02| <- CPU A15
|--01| -- GND
_______|====|
Cartridge Console
(label side) (back)
</pre>
== Mechanical details ==
{| class="wikitable"
|-
! Distance !! Length (in mm)
|-
| Distance pad to pad || 1.25
|-
| Left edge to first pad || 0.7
|-
| Last pad to right edge || 0.95
|-
| Bottom edge to longer pads (GND, Vcc) || 0.5
|-
| Bottom edge to shorter pads || 1
|}
== Signal descriptions ==
* '''/RESET''': Reset signal output from the console. On a mono WonderSwan, it stays low for about 18 milliseconds after power-up.
* '''/MBC''': Authentication handshake signal. A cartridge is required to communicate over this pin shortly after reset.
* '''M/IO''': Memory/IO bus selection. The cartridge bus allows both memory access (to physical addresses 0x10000-0xFFFFF) and I/O access (to ports 0xC0-0xFF):
** When Memory/IO is '''high''', pins A0-A19 specify the 20-bit linear memory address.
** When Memory/IO is '''low''', pins A0-A7 specify the 8-bit I/O port address, pins A8-A15 are low, pins A16-A19 are a copy of the I/O port address bits 4-7.
* '''/IRQ''': Cartridge interrupt. When this pin is pulled low, the console will trigger a maskable cartridge interrupt.
* '''CLK''': A clock provided by the console. This pin outputs a frequency of 384 KHz, derived from the 12.288 MHz system clock; on the WonderSwan Color, it can optionally be configured by software to provide a 6.144 MHz frequency instead.
== Timing requirements ==
The '''/OE''' or '''/WE''' signal appear to have a frequency of about 3.072 MHz, derived from the 12.288 MHz system clock. This leaves half this period, so about 162 ns, to handle one memory access.
TODO: Verify how using ROM/SRAM wait states affects this.
== Authentication handshake ==
Shortly after '''/RESET''' goes high, a handshake between the SoC and the cartridge is performed, in order:
* '''/MBC''' is held high. '''A0'''-'''A3''' are set to 0xA and '''A16'''-'''A19''' are set to 0x5.
* On a rising edge of '''CLK''', '''A0'''-'''A3''' are set to 0x5 and '''A16'''-'''A19''' are set to 0xA.
* The cartridge continues to hold '''/MBC''' high for three additional '''CLK''' rising edges. Note that the SoC appears to allow some variance in this number of cycles.
* For each subsequent rising edge of '''CLK''', the cartridge is expected to output the following binary sequence through its '''/MBC''' pin: <code>1000101000101000000111</code>.
* After this is finished, '''/MBC''' is expected to stay high indefinitely.
On a successful handshake, the [[SoC]] sets bit 7 of the System Control I/O port. The boot ROM will refuse to boot the cartridge if this bit is not set; on the WonderSwan Color, it will refuse to start the system at all.
An example public domain (CC0) VHDL implementation by trap15 is available [https://bitbucket.org/trap15/mbc-unlock here].
卡带dump和烧录器：up-n-atom/WonderSwanCartTap
基于VCC-GND STM32F103ZET6 Adapter Boards，这个开发板淘宝50块，可以读卡，可以烧录flash，作者有放源码，但是没打包。
卡带信息：master/hash/wswan.xml
卡带有至少3种类型，有的是sram，有的没有，有的实例：
<software name="anchorz">
<description>Anchorz Field</description>
<year>1999</year>
<publisher>Sammy</publisher>
<info name="serial" value="SWJ-SUM004"/>
<info name="release" value="19990624"/>
<info name="alt_title" value="アンカーズ・フィールド"/>
<part name="cart" interface="wswan_cart">
<feature name="pcb" value="PTE-0037" />
<feature name="u1" value="BANDAI 2001" />
<feature name="u2" value="GIZA" />你没看错，芯片叫吉萨，就是金字塔那儿
<feature name="u3" value="ROM" />
<feature name="u4" value="BS62LV256TC SRAM" />
<feature name="slot" value="ws_sram" />
<dataarea name="rom" size="1048576" width="16" endianness="little">
<rom name="mh8m256s033a.u3" size="1048576" crc="425eb893" sha1="06447c248afce04c4f4a1c3b5f7a4ab6f383c94b" offset="000000" />
</dataarea>
<dataarea name="sram" size="8192" width="16" endianness="little">
</dataarea>
</part>
</software>
<software name="cclimber">
<description>Crazy Climber</description>
<year>1999</year>
<publisher>Nihon Bussan</publisher>
<info name="serial" value="SWJ-NHB001"/>
<info name="release" value="19990729"/>
<info name="alt_title" value="クレイジー・クライマー"/>
<part name="cart" interface="wswan_cart">
<feature name="pcb" value="PTE-0012A" />
<feature name="u1" value="BANDAI 2001" />
<feature name="u2" value="empty" />
<feature name="u3" value="ROM" />
<feature name="slot" value="ws_rom" />
<dataarea name="rom" size="1048576" width="16" endianness="little">
<rom name="mh8m0e038a.u3" size="1048576" crc="0cb57376" sha1="a88882426bf435416616191902a26b2b066f2491" offset="000000" />
</dataarea>
</part>
</software>
<software name="engacho">
<description>Engacho! for WonderSwan</description>
<year>1999</year>
<publisher>Nihon Application</publisher>
<info name="serial" value="SWJ-NAP001"/>
<info name="release" value="19991028"/>
<info name="alt_title" value="えんがちょ! for ワンダースワン"/>
<part name="cart" interface="wswan_cart">
<feature name="pcb" value="PTE-0012A" />
<feature name="u1" value="BANDAI 2001" />
<feature name="u2" value="EEPROM" />
<feature name="u3" value="ROM" />
<feature name="slot" value="ws_eeprom" />
<dataarea name="rom" size="1048576" width="16" endianness="little">
<rom name="mh8m1e049a.u3" size="1048576" crc="4e467626" sha1="f79451034b6d844f0e10c825306bbc26f26a5466" offset="000000" />
</dataarea>
<dataarea name="eeprom" size="0x80" width="16" endianness="little">
</dataarea>
</part>
</software>
存档类型转换：splash5/ws-eeprom-to-sram-ips
