module erfenping(
clk_in,
rst,
clk_out
);
input clk_in;
input rst;
output clk_out;
reg clk_out;
always@(posedge clk_in or negedge rst)
if(!rst)
clk_out<=0;
else
clk_out<=~clk_out;
endmodule
`timescale 1 ps/ 1 ps
module erfenping_vlg_tst();
// constants
// general purpose registers
// test vector input registers
reg clk_in;
reg rst;
// wires
wire clk_out;
// assign statements (if any)
erfenping i1 (
// port map - connection between master ports and signals/registers
.clk_in(clk_in),
.clk_out(clk_out),
.rst(rst)
);
initial
begin
clk_in=0;
forever
#10clk_in=~clk_in;
end
initial
begin
rst=0;
#1000rst=1;
#1000;
$stop;
end
endmodule


clk_in,
rst,
clk_out
);
input clk_in;
input rst;
output clk_out;
reg clk_out;
always@(posedge clk_in or negedge rst)
if(!rst)
clk_out<=0;
else
clk_out<=~clk_out;
endmodule
`timescale 1 ps/ 1 ps
module erfenping_vlg_tst();
// constants
// general purpose registers
// test vector input registers
reg clk_in;
reg rst;
// wires
wire clk_out;
// assign statements (if any)
erfenping i1 (
// port map - connection between master ports and signals/registers
.clk_in(clk_in),
.clk_out(clk_out),
.rst(rst)
);
initial
begin
clk_in=0;
forever
#10clk_in=~clk_in;
end
initial
begin
rst=0;
#1000rst=1;
#1000;
$stop;
end
endmodule

