程序如下：
module spimaster(clk,rst,wr,datain,spics,spiclk,spido);
input clk;
input rst;
input wr;
input [7:0] datain;
output spics;
output spiclk;
output spido;
reg spics;
reg spiclk;
reg spido;
reg[7:0] cnt,dstate,dsend;
reg[1:0] spistate;
parameter idle=2'b00;
parameter send_data=2'b01;
always@(posedge clk)
begin
if(!rst)
begin
spistate<=idle;
cnt<=8'd0;
spics<=1'b1;
spiclk<=1'b1;
spido<=1'b1;
dstate<=8'd0;
end
else
begin
case(spistate)
2'b00:
begin
spics<=1'b1;
spiclk<=1'b1;
spido<=1'b1;
if(cnt==8'd40)
begin
cnt<=8'd0;
if(wr==1'b0)
begin
spistate<=send_data;
dstate<=8'd0;
dsend<=datain;
end
end
else
begin
cnt<=cnt+8'd1;
end
end
2'b01:
begin
case(dstate)
8'd0:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b1;
dstate<=8'd1;
end
8'd1:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b0;
dstate<=8'd2;
end
8'd2:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=1'b0;
dstate<=8'd3;
end
8'd3:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend[7];
dstate<=8'd4;
end
8'd4:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend[7];
dstate<=8'd5;
end
8'd5:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend[6];
dstate<=8'd6;
end
8'd6:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend[6];
dstate<=8'd7;
end
8'd7:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend[5];
dstate<=8'd8;
end
8'd8:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend[5];
dstate<=8'd9;
end
8'd9:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend[4];
dstate<=8'd10;
end
8'd10:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend[4];
dstate<=8'd11;
end
8'd11:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend[3];
dstate<=8'd12;
end
8'd12:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend[3];
dstate<=8'd13;
end
8'd13:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend[2];
dstate<=8'd14;
end
8'd14:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend[2];
dstate<=8'd15;
end
8'd15:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend[1];
dstate<=8'd16;
end
8'd16:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend[1];
dstate<=8'd17;
end
8'd17:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=dsend[0];
dstate<=8'd18;
end
8'd18:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=dsend[0];
dstate<=8'd19;
end
8'd19:
begin
spics<=1'b0;
spiclk<=1'b1;
spido<=1'b1;
dstate<=8'd20;
end
8'd20:
begin
spics<=1'b0;
spiclk<=1'b0;
spido<=1'b1;
dstate<=8'd21;
end
8'd21:
begin
spics<=1'b1;
spiclk<=1'b1;
spido<=1'b1;
spistate<=2'b00;
end
endcase
end
endcase
end
end
endmodule
testbench如下：
`timescale 1ns/1ps
module DDS_tb;
reg clk;
reg rst;
reg wr;
reg [7:0] datain;
wireclkout;
wirespics;
wirespiclk;
wirespido;
initial
begin
clk = 0;
wr = 1;
rst = 0;
#200 rst = 1;
#200 wr = 0;
#4000 wr = 1;
end
always #10 clk = ~ clk;
initial
begin
datain = 8'b0000_0000;
#500 datain = 8'b1100_1010;
#2000 $stop;
end
DDS u1(
.clk(clk),
.rst(rst),
.wr(wr),
.datain(datain),
.clkout(clkout),
.spics(spics),
.spiclk(spiclk),
.spido(spido)
);
endmodule
