【求助】assign这一句是什么意思？（Verilog语言）

module VS(SH,SL,CP60S,CPS);
output [3:0] SH;
output [3:0] SL;
output CP60S;
input CPS;
reg [3:0] SH;
reg [3:0] SL;
always @(posedge CPS)
begin
if((SH[3:0]==4'b0101)&(SL[3:0]==4'b1001))
begin SH[3:0]<=4'b0000; SL[3:0]<=4'b0000; end
else if (SL[3:0]==4'b1001)
begin SL[3:0]<=4'b0000; SH[3:0]<=SH[3:0]+1'b1; end
else
begin SH[3:0]<=SH[3:0]; SL[3:0]<=SL[3:0]+1'b1; end
end
assign CP60S=~(~SH[3]&SH[2]&~SH[1]&SH[0]&SL[3]&~SL[2]&~SL[1]&SL[0]&~CPS);
endmodule