求大神帮我看下程序

带使能信号en的译码电路
LIBRARY IEEE;<?xml:namespace prefix="o" ns="urn:schemas-microsoft-com:office:office"></?xml:namespace>
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DISPLAY IS
PORT
(EN: IN STD_LOGIC;
NUM: IN INTEGER RANGE 0 TO 15;
DISPLAY: OUT STD_LOGIC_VECTOR (0 TO 6));
END;
ARCHITECTURE DECODER OF DISPLAY IS
BEGIN
PROCESS (EN, NUM)
BEGIN
IF EN=’ 1 ’ THEN --使能信号EN为1时，译码器正常工作
CASE NUM IS
WHEN 0=>DISPLAY<=”1111110”;
WHEN 1=>DISPLAY<=”0110000”;
WHEN 2=>DISPLAY<=”1101101”;
WHEN 3=>DISPLAY<=”1111001”;
WHEN 4=>DISPLAY<=”0110011”;
WHEN 5=>DISPLAY<=”1011011”;
WHEN 6=>DISPLAY<=”0011111”;
WHEN 7=>DISPLAY<=”1110000”;
WHEN 8=>DISPLAY<=”1111111”;
WHEN OTHERS=>DISPLAY<=”0000000”;
END CASE;
ELSE
DISPLAY<=”0000000”; --EN为0，数码管无显示
END IF;
END PROCESS;
END;